1. Technical Field
This disclosure relates to nitride semiconductor devices, and particularly relates to devices including Group III nitride semiconductors which can be used as power transistors.
2. Description of the Related Art
Group III nitride semiconductors, particularly GaN and AlGaN have wide bandgaps, and thus high dielectric breakdown voltage. The Group III nitride semiconductors can readily form hetero-structures such as AlGaN/GaN. An AlGaN layer and a GaN layer generate a channel of electrons in a high concentration (two-dimensional electrons gas, 2DEG) close to the GaN layer at the interface between AlGaN and GaN because of piezo charges and a difference in bandgap between AlGaN and GaN, which are generated from a difference in lattice constant between AlGaN and GaN. Such a mechanism enables operation at large current and high speed. A device operated as an FET through control of the 2DEG channel typically refers to a high electron mobility transistor (HEMT). These properties lead to applications of the Group III nitride semiconductors to electronic devices such as power transistors such as field effect transistors (such as FET, HEMT, and HFET) and diodes.
Group III nitride semiconductors used in the power FETs have problems in gate leakage current and current collapse.
Although the gate leakage current generally refers to current flowing between a gate and a drain or between a gate and a source, the gate leakage current used in this specification is defined as a current flowing between a gate and a drain when an FET is off. The gate leakage current flowing when the FET is off has mainly three routes: (1) 2DEG leakage from the gate through 2DEG, (2) surface leak flowing from the gate through the surface of the semiconductor, and (3) barrier leak flowing from the gate through the inside a barrier layer. Besides, the gate leakage current includes substrate leak flowing between the gate and the substrate earthed. The substrate leakage will not be discussed in this specification.
Current collapse (or current slump) refers to a phenomenon generated by electrons trapped at a surface level of a semiconductor, an impurity level, or a level caused by crystal defects. Current collapse occurs as follows: The electrons trapped at one of these levels when the FET is on or off remain at the level to form a depletion layer around the level, inhibiting the drain current which should flow when the FET is on. In particular, carbon (hereinafter, referred to as C) is a known major cause to generate current collapse since carbon (hereinafter, also referred to as C) generates a deep impurity level, and electrons once trapped in such a deep level are difficult to get out from the level. Crystal growth of the Group III nitride semiconductors is typically performed by organic metal chemical vapor deposition (MOCVD). For this reason, carbon contained in the organic raw material such as trimethylgallium (TMG) or trimethylaluminum (TMA) is readily taken into crystals during the crystal growth depending on the conditions for growth.
FIG. 1 is a sectional view illustrating a structure of an FET disclosed in Japanese Unexamined Patent Application Publication No. 2013-008836. A substrate 1, a buffer layer 2, a channel layer 3 (such as GaN), and a carbon-rich or C-rich barrier layer 6 (such as AlGaN) having a bandgap larger than that of the channel layer 3 are disposed in sequence. In such a structure, a 2DEG layer 7 is generated by the difference in bandgap between the C-rich barrier layer 6 and the channel layer 3 and piezo charges in the C-rich barrier layer 6. A gate electrode 8 is disposed on the C-rich barrier layer 6, and a source electrode 9 and a drain electrode 10 in ohmic contact with each other are disposed on opposing sides of the gate electrode 8 and spaced from the gate electrode 8. The gate electrode 8 is in schottky contact with the C-rich barrier layer 6. According to Japanese Unexamined Patent Application Publication No. 2013-008836, a predetermined concentration of carbon added to the C-rich barrier layer 6 can reduce the gate leakage current, and can produce an FET having reduced current collapse.
FIG. 2 is a sectional view illustrating a structure of an FET disclosed in Japanese Unexamined Patent Application Publication No. 2014-017285. A substrate 21, a buffer layer 22, a channel layer 23 (such as GaN), and a carbon-poor or C-poor barrier layer 24 (such as AlGaN) having a bandgap larger than that of the channel layer 23 are disposed in sequence. A C-rich barrier layer 26 (such as AlGaN) containing a high concentration of carbon added by a known ion injection technique is disposed on the surface of the channel layer 23. A 2DEG layer 27 is generated in the channel layer 23 near to the interface of the C-poor barrier layer 24. A gate electrode 28 is disposed on the C-rich barrier layer 26, and a source electrode 29 and a drain electrode 30 in ohmic contact with each other are disposed on opposing sides of the gate electrode and spaced from the gate electrode 28. The gate electrode 28 is in schottky contact with the C-rich barrier layer 26. According to Japanese Unexamined Patent Application Publication No. 2014-017285, a relatively high concentration of carbon added to the C-rich barrier layer 26 can reduce the gate leakage current, and can produce an FET having reduced current collapse because no C-rich layer is disposed near the channel.
FIG. 3 is a sectional view illustrating a structure to which a diode structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-115362 is applied to an FET structure. A substrate 41, a buffer layer 42, a channel layer 43 (such a GaN), and a C-poor barrier layer 44 (such as AlGaN) having a bandgap larger than that of the channel layer 43 are disposed in sequence. A recess 45 penetrating through the C-poor barrier layer 44 into the channel layer 43 is disposed, and a C-rich barrier layer 46 (such as AlGaN) is disposed such that the recess 45 is filled with the C-rich barrier layer 46. A 2DEG layer 47 is generated in the channel layer 43 near the interface of the C-poor barrier layer 44. A gate electrode 48 is disposed such that the depression of the C-rich barrier layer 46 (such as AlGaN) is filled with the gate electrode 48, and a source electrode 49 and a drain electrode 50 in ohmic contact with each other are disposed on opposing sides of the gate electrode 48 and spaced from the gate electrode 48. The gate electrode 48 is in schottky contact with the C-rich barrier layer 46. According to Japanese Unexamined Patent Application Publication No. 2013-115362, a relatively high concentration of carbon added to the C-rich barrier layer 46 can reduce the gate leakage current.
Unfortunately, the semiconductor devices described in Technical Field have several problems in application to the field of the power transistor.
The power transistor requires normally-off operation in which the drain current does not flow at a gate voltage of the semiconductor device of 0 V (also referred to as an enhancement-mode operation) in view of the safety of apparatuses and devices on which the power transistor is mounted. The power transistor requires a very low gate leakage current. A general-purpose power semiconductor device having a rating of 600 V should not cause current collapse at 600 V.
The structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-008836, however, should have a sufficiently thin C-rich barrier layer 6 (for example, composed of 25% Al composition and having a thickness of about 5 nm) to attain a power transistor operating in a normally-off mode. A reduction in thickness of the C-rich barrier layer 6 results in an arrangement of the channel disposed closer to the surface of the semiconductor, significantly generating current collapse due to electrons trapped at the surface level. Moreover, a predetermined concentration of carbon is added to the C-rich barrier layer 6. For this reason, the carbon contained in the C-rich barrier layer 6 disposed on the channel layer 3 causes trapping of electrons at an impurity level derived from the carbon contained in the C-rich barrier layer 6, significantly generating current collapse. Accordingly, the structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-008836 cannot prevent generation of current collapse at a drain voltage of 600 V.
Similarly to the structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-008836, the C-poor barrier layer 24 and the C-rich barrier layer 26 in the structure disclosed in Japanese Unexamined Patent Application Publication No. 2014-017285 should also have a sufficiently thin total thickness (for example, composed of 25% Al composition and having a thickness of about 5 nm) to attain a power transistor operating in a normally-off mode. A reduction in thickness of the C-poor barrier layer 24 and that of the C-rich barrier layer 26 results in the channel disposed closer to the surface of the semiconductor, significantly generating current collapse due to electrons trapped at the surface level. Accordingly, the structure disclosed in Japanese Unexamined Patent Application Publication No. 2014-017285 cannot have the compatibility between the achievement of the normally-off operation and prevention in current collapse generated at 600 V. Note that unlike the structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-008836, the C-rich barrier layer 26 is disposed above the channel layer 23 without contacting the channel layer. Such a configuration can reduce the generation of current collapse to some extent if the requirement for the normally-off operation is canceled.
The structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-115362 can readily attain the normally-off operation because the recess structure is disposed immediately under the gate. Unfortunately, the edge 52 of the gate electrode having the largest electric field intensity between the gate and the drain is in contact with the thin C-rich barrier layer 46. For this reason, electrons are trapped at an impurity level derived from the carbon contained in the C-rich barrier layer 46 in contact with the channel layer 43 near the edge 52 of the gate electrode, significantly generating current collapse. Moreover, the surface leak in (2) cannot be prevented since part of the C-poor barrier layer 44 between the gate and the drain is not covered with the C-rich barrier layer 46. Accordingly, the structure disclosed in Japanese Unexamined Patent Application Publication No. 2013-115362 cannot have compatibility between the a small amount of gate leakage current and the prevention in generation of current collapse at 600 V.
The present disclosure has been made in consideration of these problems. An object of the present disclosure is to provide a nitride semiconductor device enabling normally-off operation and having reduced gate leakage current while generation of current collapse is prevented, and a method of manufacturing the nitride semiconductor device.